This tutorial shows you how the VHDL simulation flow works for Xilinx FPGA designs using MTI’s Modelsim simulator. The design, watch, targets a Virtex device and implements the functionality of a typical runner’s stopwatch. This tutorial contains the following sections.
- Design Description
- Before Beginning the Tutorial
- Tutorial Installation
- Including CoreGen Components
- Creating the Tenths CORE Generator Component
- Synthesizing/Implementing the design
- Timing Simulation
Throughout this tutorial, the design is referred to as Watch which is a design for a runner’s stop watch. The tutorial assumes that you have a working knowledge of VHDL. The Watch design is a counter that counts up from 0 to 59, then resets to zero, and starts over. There are three external inputs and three external outputs in the completed design.
