This tutorial is an introduction to the Synopsys Behavioral Compiler. It shows you the advantages of technology-independent and architecture-independent behavioral designing methodology and
- How to start and use Behavioral Compiler
- How to use BCView to graphically analyze a design
- How to code for synthesis
- How to simulate a design for pre-synthesis and post-synthesis verification
- Synthesis with Verilog
- Synthesis with VHDL
- Coding for Synthesis with Verilog
- Coding for Synthesis with VHDL
- Simulation
- Some Final Thoughts
The synthesis lab session shows you the steps to synthesize a relatively simple design to RTL. Then it shows you how to analyze the design using BCView. The complex number multiplier design was chosen for two purposes: 1) it is an easy circuit to understand, 2) it compiles quickly so the lab session is relatively fast moving with quick compilations.
You provide a Verilog or VHDL behavioral description of the desired function, such as a complex multiplier or FFT chip. The main difference between behavioral Verilog/VHDL code and implementation-specific (RTL) code is that the behavioral code can, and should, describe only the function and not be tied to any particular architecture or technology. After you perform the steps through the schedule stage that implements details such as technology and architecture, the trade-offs of circuit throughput versus chip size versus clock period come into play. When you resolve those issues, you can compile the design into cycle-accurate HDL and create a cycle-accurate database for simulation or a gate-level netlist. Then you can simulate at the behavioral, RTL, and gate levels to ensure the final implementation functions as intended. The illustration below depicts these tradeoffs.
You provide a Verilog or VHDL behavioral description of the desired function, such as a complex multiplier or FFT chip. The main difference between behavioral Verilog/VHDL code and implementation-specific (RTL) code is that the behavioral code can, and should, describe only the function and not be tied to any particular architecture or technology. After you perform the steps through the schedule stage that implements details such as technology and architecture, the trade-offs of circuit throughput versus chip size versus clock period come into play. When you resolve those issues, you can compile the design into cycle-accurate HDL and create a cycle-accurate database for simulation or a gate-level netlist. Then you can simulate at the behavioral, RTL, and gate levels to ensure the final implementation functions as intended. The illustration below depicts these tradeoffs.
