Part 1 Primary Design Unit Model Structure
- Entity Declaration Format
- Architecture
- Declaration and Libraries
- Identifiers, Numbers, Strings, and Expressions
- Data Types
- Objects: Signals, Constants, and Variables
- Concurrent Statements
- Signal Assignment
- Process Statement
- Block Statement
- Procedure Statement
- Component Instantiation
- Concurrent Assertion
- Generate Statement
- Sequential Statements
- Wait Statement
- Signal Assignment
- Variable Assignment
- Procedure Call
- Conditional Statements
- Loop Statements
- Procedure Statement
- Function Statement
- Other IEEE "std.logic" Functions
- Object Attributes
- The TEXTIO Package
Each VHDL design unit comprises an "entity" declaration and one or more "architectures". Each architecture defines a different implementation or model of a given design unit. The entity definition defines the inputs to, and outputs from the module, and any "generic" parameters used by the different implementations of the module. A VHDL package contains subprograms, constant definitions, and/or type definitions to be used throughout one or more design units. Identifiers in VHDL must begin with a letter, and may comprise any combination of letters, digits, and underscores. Note that VHDL internally converts all characters to UPPER CASE. Expressions in VHDL are similar to those of most high-level languages. Data elements must be of the type, or subtypes of the same base type. Each VHDL objects must be classified as being of a specific data type. VHDL includes a number of predefined data types, and allows users to define custom data types as needed.
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