VHDL Development System and Coding Standard

With the growing complexity of todays ASICs and the number of designers involved in one VHDL ASIC project, the need for a VHDL development system together with coding rules for simulation and synthesis has emerged.

This paper describes the VHDL Coding Standard which has been established and the VHDL development system including code entry, code formatting, code compliance checkers, data management and multi-user project set-up.

Designing ASICs for telecommunication applications like SDH (“Synchronous Digital Hierarchy”), ATM (“Asynchronous Transfer Mode”), Subscriber access and GSM (“Global System for Mobile communication”) results in design complexities of half a million logic gates and code development of more than a hundred thousand lines of code for VHDL testbenches, behavioral level modeling for simulation and RT-level for synthesis.

The project teams, creating those complex designs, need definitely assistance in a common set of rules to apply and in tool support apart from a VHDL simulator and synthesis tool. While the expressive power, flexibility, technology and process independence and the ability of coding on different abstraction levels [1],[4] significantly contributes to the success of VHDL, these qualities may cause on the other hand severe problems, when experience and project coordination is insufficient. Potential problems are exchangeability, portability, reusability, understanding of all available language constructs and unexpected behavior in simulation and in synthesis results.

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Gray counter in VHDL

This paper presents the simple structural description of the Gray counter with variable width in VHDL.

Programmable logic devices (PLDs) and field programmable gate arrays (FPGAs) can be used to integrate large amounts of logic in a single IC. As the capacity of PLDs and FPGAs is grooving, designers can no longer use Boolean equations or gate-level descriptions to quickly and efficiently complete a design. The solution is VHDL. Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) became standard for designing with programmable logic devices and Application Specific Integrated Circuits (ASICs). VHDL was established as the IEEE 1706 standard in 1987. The main advantage of VHDL is portability of code across vendors and devices. The main disadvantage is the loosing control of gate level circuit implementation, which is the penalty for portability.

Gray code is the code with only one bit transition between adjacent words. The direct description of Gray counter is based on the equation extraction from the truth table. Such solution of n-bit counter demands 2n-2 product terms. Implementation may be difficult for greater width of counter. The alternative is the using of the auxiliary bit. This bit is changed every clock period and corresponds to bit 0 of a binary counter. With assumption that the auxiliary bit extends Gray code word to the right, the particular bit is changed whenever the less significant bits create word 1,0,…0. The exception is MSB which is changed in addition by word 0,…0. Another description of Gray counter use conversion of Gray code to binary code. After the increment is done in binary code, the back conversion follows.

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VHDL: A Tutorial By Mani B. Srivastava

By Mani B. Srivastava

This VHDL tutorial contains following topics

• Introduction to the language and simple examples
• VHDL’s model of a system - its computation model: processes, signals and time
• Language features
• VHDL for logic and queue simulation

WHAT IS VHDL?

• VHDL is Programming Language used as Hardware Modelling Language.
• It has all of the following:
• Sequential Procedural language: PASCAL and ADA like
• Concurrency: statically allocated network of processes
• Timing constructs
• Discrete-event simulation semantics
• Object-oriented goodies: libraries, packages, polymorphism

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VHDL Basic I/O

By Erkay Savaş
Sabancı University

VHDL Basic I/O and Its Applications

Objects of file type – it is a special type that serve as an interface between the VHDL programs and the host environment.
Motivation – how file objects are created, read, written and used within VHDL simulations
To get it right – File input and output cannot be synthesized, I/O operations do not refer to I/O pins of FPGA chips

Test Benches with File Object

Test bench – VHDL programs for testing VHDL models. A typical test bench reads test inputs from a file, applies them to the VHDL model under test and records model outputs for analysis.

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The VHDL Golden Reference Guide

The VHDL Golden Reference Guide is a compact quick reference guide to the VHDL language, its syntax, semantics, synthesis and application to hardware design.

The VHDL Golden Reference Guide is not intended as a replacement for the IEEE Standard VHDL Language Reference Manual. Unlike that document, the Golden Reference guide does not offer a complete, formal description of VHDL. Rather, it offers answers to the questions most often asked during the practical application of VHDL, in a convenient reference format.

Nor is The VHDL Golden Reference Guide intended to be an introductory tutorial. Information is presented here in a terse reference format, not in the progressive and sympathetic manner necessary to learn a subject as complex as VHDL. However, acknowledging that those already familiar with computer languages may wish to use this guide as a VHDL text book, a brief informal introduction to the subject is given at the start.

The main feature of The VHDL Golden Reference Guide is that it embodies much practical wisdom gathered over many VHDL projects. It does not only provide a handy syntax reference; there are many similar books which perform that task adequately. It also warns you of the most common language errors, gives clues where to look when your code will not compile, alerts you to synthesis issues, and gives advice on improving your coding style.

The VHDL Golden Reference Guide was developed to add value to the Doulos range of VHDL training courses, and also to complement VHDL PaceMaker, the VHDL Computer Based Training package from Doulos.

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A structured VHDL design method

By Jiri Gaisler

The VHDL language was developed to allow modelling of digital hardware. It can be seen as a super-set of Ada, with a built-in message passing mechanism called signals. The language was defined in the mid-1980’s as a respons to the difficulties of developing, validating and co-simulating increasingly complex digital devices developed within the VHSIC program. The main focus was to be able to write executable specifications, and allow specifications (or models) from different providers (companies) to be simulated together.

When the language was first put to use, it was used for high-level behavioural simulation only. ’Synthesis’ into VLSI devices was made by manually converting the models into schematics using gates and building blocks from a target library. However, manual conversion tended to be error-prone, and was likely to invalidate the effort of system simulation. To address this problem, VHDL synthesis tools that could convert VHDL code directly to a technology netlist started to emerge on the market in the begining of 1990’s. Since the VHDL code could now be directly synthesised, the development of the models was primarily made by digital hardware designers rather than software engineers. The hardware engineers were used to schematic entry as design method, and their usage of VHDL resembled the dataflow design style of schematics. The functionality
was coded using a mix of concurrent statments and short processes, each decribing a limited piece of functionality such as a register, multiplexer, adder or state machine. In the early 1990’s, such a design style was acceptable since the complexity of the circuits was relatively low (< 50 Kgates) and the synthesis tools could not handle more complex VHDL structures. However, today the device complexity can reach several millions of gates, and the synthesis tools accept a much larger part of the VHDL standard. It should therefore be possible to use a more modern and efficient VHDL design method than the traditional ’dataflow’ version. This chapter will describe such a method and compare it to the ’dataflow’ version.

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ModelSim VHDL Simulation Tutorial

This tutorial shows you how the VHDL simulation flow works for Xilinx FPGA designs using MTI’s Modelsim simulator. The design, watch, targets a Virtex device and implements the functionality of a typical runner’s stopwatch. This tutorial contains the following sections.

• Design Description
• Before Beginning the Tutorial
• Tutorial Installation
• Including CoreGen Components
• Creating the Tenths CORE Generator Component
• Synthesizing/Implementing the design
• Timing Simulation

Design Description

Throughout this tutorial, the design is referred to as Watch which is a design for a runner’s stop watch. The tutorial assumes that you have a working knowledge of VHDL. The Watch design is a counter that counts up from 0 to 59, then resets to zero, and starts over. There are three external inputs and three external outputs in the completed design.

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VHDL From Wikipedia, the free encyclopedia

VHDL (VHSIC hardware description language; VHSIC: very-high-speed integrated circuit) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.

VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details.

The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest area, lowest power consumption, highest clock speed, or other requirements.

VHDL borrows heavily from the Ada programming language in both concepts (for example, the slice notation for indexing part of a one-dimensional array) and syntax. VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is strongly typed and is not case sensitive. There are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor, in order to directly represent operations which are common in hardware. VHDL also allows arrays to be indexed in either direction (ascending or descending) because both conventions are used in hardware, whereas Ada (like most programming languages) provides ascending indexing only. The reason for the similarity between the two languages is that the Department of Defense required as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada.

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VHDL quick Start

By Peter J Ashenden

You will learn quick introduction to VHDL such as basic VHDL language concepts, basic VHDL design methodology and this will be a great reference for VHDL project works.

Following are the few topic covered in this VHDL quick start guide

• Modeling Digital Systems
• Domains and Levels of Modeling
• Basic VHDL Concepts
• Modeling Interfaces
• Modeling Behavior
• Behavior Example
• VHDL-87
• Modeling Structure
• Structure Example in VHDL-87
• Mixed Behavior and Structure
• Test Benches
• Test Bench Example
• Regression Testing
• Regression Test Example
• Design Processing
• Analysis
• Elaboration
• Elaboration Example
• Simulation
• Simulation Algorithm
• Synthesis
• Basic Design Methodology

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Behavioral Compiler Tutorial

This tutorial is an introduction to the Synopsys Behavioral Compiler. It shows you the advantages of technology-independent and architecture-independent behavioral designing methodology and

• How to start and use Behavioral Compiler
• How to use BCView to graphically analyze a design
• How to code for synthesis
• How to simulate a design for pre-synthesis and post-synthesis verification

Following are the few topics covered in this VHDL tutorial

• Synthesis with Verilog
• Synthesis with VHDL
• Coding for Synthesis with Verilog
• Coding for Synthesis with VHDL
• Simulation
• Some Final Thoughts

Synthesis with VHDL

The synthesis lab session shows you the steps to synthesize a relatively simple design to RTL. Then it shows you how to analyze the design using BCView. The complex number multiplier design was chosen for two purposes: 1) it is an easy circuit to understand, 2) it compiles quickly so the lab session is relatively fast moving with quick compilations.

You provide a Verilog or VHDL behavioral description of the desired function, such as a complex multiplier or FFT chip. The main difference between behavioral Verilog/VHDL code and implementation-specific (RTL) code is that the behavioral code can, and should, describe only the function and not be tied to any particular architecture or technology. After you perform the steps through the schedule stage that implements details such as technology and architecture, the trade-offs of circuit throughput versus chip size versus clock period come into play. When you resolve those issues, you can compile the design into cycle-accurate HDL and create a cycle-accurate database for simulation or a gate-level netlist. Then you can simulate at the behavioral, RTL, and gate levels to ensure the final implementation functions as intended. The illustration below depicts these tradeoffs.

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VHDL reference material

Following are the free VHDL reference materials provided by csee.umbc.edu.

Contents

• Using Cadence VHDL on CSEE machine
• Compact Summary of VHDL
• Printable Compact Summary of VHDL
• Sample VHDL code
• VHDL-handbook.pdf
• VHDL designers guide
• VHDL Cookbook in PostScript
• GHDL Download free VHDL compiler and simulator
• Download free VHDL compiler and simulator
• VHDL intro by Francis Bruno in PostScript
• VHDL project by Francis Bruno in PostScript
• VCOMP/VSIM from University of Pittsburgh
• Using FTL Systems Exploration VHDL
• VHDL standard packages and types
• FPGA and other CAD information
• Draft of IEEE Standard VHDL Language 

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Analog and Mixed-Signal Modeling Using the VHDL-AMS Language

What is VHDL-AMS

IEEE Std. 1076-1993: VHDL (VHSIC Hardware Description Language) supports the description and simulation of event-driven systems.

IEEE Std. 1076.1-1999: Extension to VHDL to support the description and simulation of analog and mixed-signal circuits and systems

IEEE Std. 1076.1-1999 together with IEEE Std. 1076-1993 is informally known as VHDL-AMS.

VHDL-AMS is a strict superset of IEEE Std. 1076-1993: Any model valid in VHDL 1076 is valid in VHDL-AMS and yields the same simulation results

Why is VHDL-AMS needed?

VHDL 1076 is suitable for modeling and simulating discrete systems. Designers want a uniform description language and Many of today’s designs include at least some continuous characteristics such as

System design

• Mixed-signal electrical designs
• Mixed electrical/non-electrical designs
• Modeling design environment

Analog design

• Analog behavioral modeling and simulation

Digital design

• Detailed modeling (e.g. submicron effects)

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VHDL Modelling Guidelines

Prepared by P. Sinander

This document defines requirements on VHDL models and testbenches, and is intended to be used as an applicable document for ESA developments involving VHDL modelling. It is mainly focused on digital models; specific requirements for analog modelling have not been covered.

The requirements concern simulation and documentation aspects of VHDL models delivered to ESA; specific rules and guidelines for logic synthesis from VHDL have not been included. Nevertheless, the requirements of this document are compatible with the use of logic synthesis. The requirements are not applicable for the case when a design database is transferred in VHDL format.

The purpose of these requirements is to ensure a high quality of the developed VHDL models, so they can be efficiently used and maintained with a low effort throughout the full life-cycle of the modelled hardware.

The requirements are based on the VHDL-93 standard, to minimise future maintenance efforts for updating models. However, in an initial stage the models shall be backward compatible with VHDL-87 as far as possible, since some tools will not be updated immediately.

The requirements have been structured in a general part applicable to all VHDL models, and additional requirements applicable to different kinds of models. In addition, VHDL code examples and a list of common problems encountered have been included in order to provide some guidance to the VHDL developer. If not stated which kind of model is to be developed, the default kind is a model for Component simulation.

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VHDL Tutorial By Jan Van der Spiegel

By Jan Van der Spiegel

This tutorial gives a brief overview of the VHDL language and is mainly intended as a companion for the Digital Design Laboratory. This writing aims to give the reader a quick introduction to VHDL and to give a complete or in-depth discussion of VHDL. For a more detailed treatment, please consult any of the many good books on this topic. Several of these books are listed in the reference list.

Introduction
VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. In the mid-1980’s the U.S. Department of Defense and the IEEE sponsored the development of this hardware description language with the goal to develop very high-speed integrated circuit. It has become now one of industry’s standard languages used to describe digital systems. The other widely used hardware description language is Verilog. Both are powerful languages that allow you to describe and simulate complex digital systems.  A third HDL language is ABEL (Advanced Boolean Equation Language) which was specifically designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two languages and is less popular in industry. This tutorial deals with VHDL, as described by the IEEE standard 1076-1993.

Although these languages look similar as conventional programming languages, there are some important differences. A hardware description language is inherently parallel, i.e. commands, which correspond to logic gates, are executed (computed) in parallel, as soon as a new input arrives. A HDL program mimics the behavior of a physical, usually digital, system. It also allows incorporation of timing specifications (gate delays) as well as to describe a system as an interconnection of different components.

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VHDL Tutorial By Wolfram H. Glauert

By Wolfram H. Glauert

VHDL is a hardware description language. The word 'hardware', however, is used in a wide variety of contexts which range from complete systems like personal computers on one side to the small logical gates on their internal integrated circuits on the other side.

This is why different descriptions exist for the hardware functionality. Complex systems are often described by the behaviour that is observable from the outside. Abstract behavioural models are used in this case that hide all the implementation details. In this example the print protocol will be executed whenever a PRINTREQUEST occurs. This can be either a pressed key or a software command, etc. The description of a basic logic gate, on the other hand, may consist of only one boolean equation. This is a very short and precise description.

The language VHDL covers the complete range of applications and can be used to model (digital) hardware in a general way.

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VHDL Tutorial: Learn by Example

by Weijun Zhang

HDL (Hardware Description Language) based design has established itself as the modern approach to design of digital systems, with VHDL (VHSIC Hardware Description Language) and Verilog HDL being the two dominant HDLs. Numerous universities thus introduce their students to VHDL (or Verilog). The problem is that VHDL is complex due to its generality. Introducing students to the language first, and then showing them how to design digital systems with the language, tends to confuse students. The language issues tend to distract them from the understanding of digital components. And the synthesis subset issues of the language add to the confusion.

We developed the following tutorial based on the philosophy that the beginning student need not understand the details of VHDL -- instead, they should be able to modify examples to build the desired basic circuits. Thus, they learn the importance of HDL-based digital design, without having to learn the complexities of HDLs. Those complexities can be reserved for a second, more advanced course. The examples are mostly from the textbook Embedded System Design by Frank Vahid and Tony Givargis. They start from basic gates and work their way up to a simple microprocessor. Most of the examples have been simulated by Aldec ActiveHDL Simulator and Synopsys Design Analyzer, as well as synthesized with Synopsys Design Compiler. Several sequential design examples have been successfully tested on Xilinx Foundation Software and FPGA/CPLD board.

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VHDL Mini reference

VHDL Mini-Reference can be divided into the following parts:

Part 1 Primary Design Unit Model Structure

• Entity Declaration Format
• Architecture

Part 2 Packages

• Declaration and Libraries
• Identifiers, Numbers, Strings, and Expressions
• Data Types
• Objects: Signals, Constants, and Variables
• Concurrent Statements
• Signal Assignment
• Process Statement
• Block Statement
• Procedure Statement
• Component Instantiation
• Concurrent Assertion
• Generate Statement
• Sequential Statements
• Wait Statement
• Signal Assignment
• Variable Assignment
• Procedure Call
• Conditional Statements
• Loop Statements
• Procedure Statement
• Function Statement
• Other IEEE "std.logic" Functions
• Object Attributes
• The TEXTIO Package 

 Each VHDL design unit comprises an "entity" declaration and one or more "architectures". Each architecture defines a different implementation or model of a given design unit. The entity definition defines the inputs to, and outputs from the module, and any "generic" parameters used by the different implementations of the module. A VHDL package contains subprograms, constant definitions, and/or type definitions to be used throughout one or more design units. Identifiers in VHDL must begin with a letter, and may comprise any combination of letters, digits, and underscores. Note that VHDL internally converts all characters to UPPER CASE. Expressions in VHDL are similar to those of most high-level languages. Data elements must be of the type, or subtypes of the same base type. Each VHDL objects must be classified as being of a specific data type. VHDL includes a number of predefined data types, and allows users to define custom data types as needed.

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An Introductory VHDL Tutorial

By Green Mountain Computing Systems

Welcome to our online VHDL tutorial! The VHDL tutorial has been separated into chapters and sections to provide easy access for second time visitors. However, the tutorial was designed to be presented in sequence and should be read as such. To follow the tutorial sequentially, simply follow the next section link at the end of each page.

Directory of Chapters

• An Introduction and Background
• Structural Descriptions
• Data Flow Descriptions
• Behavioral Descriptions

VHDL is an acronym which stands for VHSIC Hardware Description Language. VHSIC is yet another achronym which stands for Very High Speed Integrated Circuits. If you can remember that, then you're off to a good start. The language has been known to be somewhat complicated, as its title (as titles go). The acronym does have a purpose, though; it is supposed to capture the entire theme of the language, that is to describe hardware much the same way we use schematics.

VHDL can wear many hats. It is being used for documentation, verification, and synthesis of large digital designs. This is actually one of the key features of VHDL, since the same VHDL code can theoretically achieve all three of these goals, thus saving a lot of effort. In addition to being used for each of these purposes, VHDL can be used to take three different approaches to describing hardware. These three different approaches are the structural, data flow, and behavioral methods of hardware description. Most of the time a mixture of the three methods are employed. The following sections introduce you to the language by examining its use for each of these three methodologies. There are also certain guidelines that form an approach to using VHDL for synthesis, which is not addressed by this tutorial.

VHDL is a standard (VHDL-1076) developed by IEEE (Institute of Electrical and Electronics Engineers). The language has been through a few revisions, and you will come across this in the VHDL community. Currently, the most widely used version is the 1987 (std 1076-1987) version, sometimes referred to as VHDL'87, but also just VHDL. However, there is a newer revision of the language referred to as VHDL'93. VHDL'93 (adopted in 1994 of course) is fairly new and is still in the process of replacing VHDL'87.

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Guide to Synthesis and Implementation Tools for VHDL Modeling and Design

This is a VHDL guide to know more about VHDL synthesis, simulation and implementation tools.  Following are the few topics covered in this VHDL book.

• VHDL Design Process
• VHDL Tools
• Xilinx Synopsys Interface
• Simulation and Verification (RTL)
• Synthesis
• Place and Route
• Simulation and Verification (PPR)
• Hardware Realization
• Design Entry Considerations
• Other Sources of Documentation
• User Directory Setup
• RTL Verification
• Setup Conditions
• Generating LogiBloX Primitives
• Testbench Requirements
• Compiling Simulation
• Waveform Analisys and Debbuging
• Synthesis
• Setup Conditions
• FPGA Analyzer
• Synthesis Script
• Component List
• Reading Design Components
• LogiBloX Issues
• Setting Initial Constraints
• Compiling and Generating Reports
• XILINX Specific Issues
• Startup Block
• Internal Global Buffers 
• Place and Route
• Post Place and Route Verification
• Compilation Script
• Simulation Script
• Implementation 

About this Guide
By Martin Rosner 

During the course of my MS thesis I had the less than pleasant opportunity to learn the tools used for VHDL synthesis, simulation and implementation. Together with a colleague of mine, Jens-Peter Kaps, we managed to set up libraries and run the appropriate tools in order to realize our designs. In this case, the word `realize' encompasses many stages of the development for which different tools had to be installed and utilized. The generous help of our sys-admin guys, Brady Schulman and Murtaza Amiji was crucial during this setup and installation stage. In this document, I will try to describe the process that we used to realize a conceivable digital design. This document is not intended to be 100$\%$ thorough and should be used as an initial guide to the synthesis, simulation and implementation tools. Most of the information presented here can be found in the online documentation provided by the vendors. My job here is just to summarize the most important and the hard to find information regarding the setup and utilization of these tools. For a more formal and more complete source of information, the reader is directed to the vast number of manuals that exist and are available online or in the crypto lab. Whenever appropriate, I will try to point out the particular documentation manual and describes a certain subject in greater detail.

In this chapter, I will give a general description of the process that we used to realize our designs. I will also briefly describe our main method of design entry and some of the more important considerations associated with VHDL entry and synthesis. Each consecutive chapter after this one will describe one step of the process and the tools associated with this step. Thus if you just want to learn about synthesis you should refer to Chapter 3 that describes the Synopsys tools that we used to perform synthesis.

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The VHDL Cookbook

By Peter J. Ashenden

VHDL is a language for describing digital electronic systems. It arose out of the United States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. In the course of this program, it became clear that there was a need for a standard language for describing the structure and function of integrated circuits (ICs). Hence the VHSIC Hardware Description Language (VHDL) was developed, and subsequently adopted as a standard by the Institute of Electrical and Electronic Engineers (IEEE) in the US.

VHDL is designed to fill a number of needs in the design process. Firstly, it allows description of the structure of a design, that is how it is decomposed into sub-designs, and how those sub-designs are interconnected. Secondly, it allows the specification of the function of designs using familiar programming language forms. Thirdly, as a result, it allows a design to be simulated before being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping.

The purpose of this booklet is to give you a quick introduction to VHDL. This is done by informally describing the facilities provided by the language, and using examples to illustrate them. This booklet does not fully describe every aspect of the language. For such fine details, you should consult the IEEE Standard VHDL Language Reference Manual. However, be warned: the standard is like a legal document, and is very difficult to read unless you are already familiar with the language. This booklet does cover enough of the language for substantial model writing. It assumes you know how to write computer programs using a conventional programming language such as Pascal, C or Ada.

The remaining chapters of this booklet describe the various aspects of VHDL in a bottom-up manner. Chapter2 describes the facilities of VHDL which most resemble normal sequential programming languages. These include data types, variables, expressions, sequential statements and subprograms. Chapter3 then examines the facilities for describing the structure of a module and how it it decomposed into sub-modules. Chapter4 covers aspects of VHDL that integrate the programming language features with a discrete event timing model to allow simulation of behaviour. Chapter5 is a key chapter that shows how all these facilities are combined to form a complete model of a system. Then Chapter6 is a potpourri of more advanced features which you may find useful for modeling more complex systems.

Throughout this booklet, the syntax of language features is presented in Backus-Naur Form (BNF). The syntax specifications are drawn from the IEEE VHDL Standard. Concrete examples are also given to illustrate the language features. In some cases, some alternatives are omitted from BNF productions where they are not directly relevant to the context. For this reason, the full syntax is included in AppendixA, and should be consulted as a reference.

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VHDL Starters Guide

By Sudhakar Yalamanchili

This text focuses on presenting the basic features of the VHDL language in the context of its use for simulation. The text is targeted for use in sophomore and junior level courses in digital logic and computer architecture. The style of this text is intended to permit integration of the basic concepts underlying VHDL into existing courses without necessitating additional credit hours or courses for instruction. In order to fill the need for a companion text for digital logic and computer architecture courses and to serve as an early introduction to the basic language concepts the book must satisfy several criteria. First, it must relate VHDL concepts to those already familiar to the student. Students learn best when they can relate new concepts to ones with which they are already familiar. In this case we rely on concepts from the operation of digital circuits. Language features are motivated by the need to describe specific aspects of the operation of digital circuits, for example, events, propagation delays, and concurrency.

Chapter 1: Introduction
This chapter provides a very brief introduction to the place hardware description languages employ in a typical digital system design flow and the genealogy of VHDL.

Chapter 2 : Simulation of Digital Systems
VHDL language constructs can be related to digital system concepts that we are already familiar with. This chapter lists fundamental physical and behavioral  attributes of  digital systems. Language constructs to describe each attribute will be introduced in subsequent chapters. The chapter concludes with a description of the discrete event execution model that underlies the execution of the VHDL programs.

Chapter 3: Basic Language Concepts:
Basic language constructs are introduced by associating each construct with a physical or behavioral attribute of digital systems. Existing knowledge of digital systems is naturally transformed into executable VHDL descriptions.

Chapter 4: Modeling Behavior:
In describing very large systems we often wish to abstract or hide the details of digital logic implementation while preserving the external behavior. Such a modeling approach can be achieved in VHDL with higher level language constructs structured in processes.

Chapter 5: Modeling Structure
The use of hierarchy and abstraction is necessary to handle large designs and consequently requires the introduction of  new language constructs. A hierarchy of netlists is a standard representation in traditional digital design  tools and VHDL provides language constructs for a textual description of such a hierarchy.

Chapter 6: Subprograms, Packages, and Libraries
Abstraction is enabled in VHDL via standard programming language concepts such as procedures, functions, packages and libraries to enable design re-use, sharing, and ease of maintenance.

Chapter 7: Basic Input/Output
Text file input/output mechanisms are used to enable the integration of the results of test generation tools and the VHDL models under test. Basic error checking and testbench generation techniques are also covered.

Chapter 8:  Programming Mechanics
This chapter provides an intuition about the practical aspects of VHDL environments: the terminology and mechanics of organizing, building, simulating VHDL models.

Chapter 9: Identifiers, Data Types, and Operators
A quick reference guide to the basic language syntax.

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