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Gray counter in VHDL

This paper presents the simple structural description of the Gray counter with variable width in VHDL.

Programmable logic devices (PLDs) and field programmable gate arrays (FPGAs) can be used to integrate large amounts of logic in a single IC. As the capacity of PLDs and FPGAs is grooving, designers can no longer use Boolean equations or gate-level descriptions to quickly and efficiently complete a design. The solution is VHDL. Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) became standard for designing with programmable logic devices and Application Specific Integrated Circuits (ASICs). VHDL was established as the IEEE 1706 standard in 1987. The main advantage of VHDL is portability of code across vendors and devices. The main disadvantage is the loosing control of gate level circuit implementation, which is the penalty for portability.

Gray code is the code with only one bit transition between adjacent words. The direct description of Gray counter is based on the equation extraction from the truth table. Such solution of n-bit counter demands 2n-2 product terms. Implementation may be difficult for greater width of counter. The alternative is the using of the auxiliary bit. This bit is changed every clock period and corresponds to bit 0 of a binary counter. With assumption that the auxiliary bit extends Gray code word to the right, the particular bit is changed whenever the less significant bits create word 1,0,…0. The exception is MSB which is changed in addition by word 0,…0. Another description of Gray counter use conversion of Gray code to binary code. After the increment is done in binary code, the back conversion follows.

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