With the growing complexity of todays ASICs and the number of designers involved in one VHDL ASIC project, the need for a VHDL development system together with coding rules for simulation and synthesis has emerged.
This paper describes the VHDL Coding Standard which has been established and the VHDL development system including code entry, code formatting, code compliance checkers, data management and multi-user project set-up.
Designing ASICs for telecommunication applications like SDH (“Synchronous Digital Hierarchy”), ATM (“Asynchronous Transfer Mode”), Subscriber access and GSM (“Global System for Mobile communication”) results in design complexities of half a million logic gates and code development of more than a hundred thousand lines of code for VHDL testbenches, behavioral level modeling for simulation and RT-level for synthesis.
The project teams, creating those complex designs, need definitely assistance in a common set of rules to apply and in tool support apart from a VHDL simulator and synthesis tool. While the expressive power, flexibility, technology and process independence and the ability of coding on different abstraction levels [1],[4] significantly contributes to the success of VHDL, these qualities may cause on the other hand severe problems, when experience and project coordination is insufficient. Potential problems are exchangeability, portability, reusability, understanding of all available language constructs and unexpected behavior in simulation and in synthesis results.
